The main objective of this work is to enhance the processing performance of the recently introduced video
codec H. 265/HEVC. Since most of the computations of H. 265/HEVC still occur in the motion estimation
engine which is inherited from its predecessor H.264/AVC, we propose a bit-shrinking approach with a
modified logic functionality to design an efficient and simplified block matching unit that replaces the
already used Sum of Absolute Differences (SAD) unit. The hardware complexity of the proposed unit itself
is reduced and the number of its generated output bits is reduced as well which in turn simplifies all the
subsequent units of motion estimation. The hardware complexity, the consumed power and the processing
delay of the motion estimation engine are therefore reduced significantly with only marginal
deterioration in both the bit-rate and the peak-signal-to-noise-ratios (PSNR) of the tested High Definition
(HD) and Ultra-High Definition (UHD) H.265/HEVC compressed videos. We simulate our design using
HM16.6 and perform system logic synthesis using Synopsys’s Design Compiler, targeting ASIC, for
Advanced Video Coding, Rec. ITU-T H.264 and ISO/IEC 14496-10, 2014.
High Efficiency Video Coding, Rec. ITU-T H.265 and ISO/IEC 23008-2, 2015.
D. Grois et al., "Performance Comparison of H. 265/MPEG-HEVC, VP9 and H. 264/MPEG- AVC Encoders," Proc. Picture Coding Symp., pp. 394-397, 2013.
VP9, WebM Project's Next-generation Open Video Codec, 2013.
Y. Li, J. Xiao and W. Wu, "Motion Estimation Based on H.264 Video Coding," Proc. 5th Int. Congress Image and Signal Process., pp. 104-108, 2012.
M.U.K. Khan, M. Shafique and J. Henkel, "AMBER: Adaptive Energy Management for On-chip Hybrid Video Memories," Proc. IEEE/ACM Int. Conf. Computer-Aided Design, pp. 405-412, 2013.
R. Li, B. Zeng and M.L. Liou, "A New Three-step Search Algorithm for Block Motion Estimation," IEEE Trans. Circuits Syst. Video Technol., vol. 4, no. 4, pp. 438-442, August 1994.
L. M. Po and W. C. Ma, "A Novel Four Step Search Algorithm for Fast Block Motion Estimation," IEEE Trans. Circuits Syst. Video Technol., vol. 6, no. 3, pp. 313–317, June 1996. 151 Jordanian Journal of Computers and Information Technology (JJCIT), Vol. 2, No. 2, August 2016.
C. Zhu et al., "A Novel Hexagon-based Search Algorithm for Fast Block Motion Estimation," Proc. Int. Conf. Acoustics, Speech and Signal Process., pp. 1593–1596, 2001.
S. Zhu and K.K. Ma, "A New Diamond Search Algorithm for Fast Block-matching Motion Estimation," IEEE Trans. Image Process., vol. 9, no. 2, pp. 287–290, Feburuary 2000.
Y. Nie and K. K. Ma, "Adaptive Rood Pattern Search for Fast Block-matching Motion Estimation," IEEE Trans. Image Process., vol. 11, no. 12, pp. 1442–1448, December 2002.
J. Olivaresa et al., "SAD Computation Based on Online Arithmetic for Motion Estimation," Elsevier Microprocessors and Microsystems, vol. 30, no. 5, pp. 250–258, August 2006.
T. H. Tran, H. M. Cho and S. B. Cho, "Performance Enhancement of Sum of Absolute Difference (SAD) Computation in H.264/AVC Using Saturation Arithmetic," Proc. Emerging Intelligent Computing Technol. and Applicat., pp. 396–404, 2009.
J. Vanne et al., "A High-performance Sum of Absolute Difference Implementation for Motion Estimation," IEEE Trans. Circuits Syst. Video Technol., vol. 16, no. 7, pp. 876-883, July 2006.
S. Lee, J. M. Kim and S. I. Chae, "New Motion Estimation Algorithm Using Adaptively Quantized Low Bit Resolution Image and Its VLSI Architecture for MPEG2 Video Encoding," IEEE Trans. Circuits Syst. Video Technol., vol. 8, no. 6, pp. 734–744, October 1998.
H. Yeo and Y. H. Hu, "A Novel Architecture and Processor-level Design Based on a New Matching Criterion for Video Compression," Proc. IEEE Workshop on VLSI Signal Process. IX, pp. 448–457, 1996.
S. Ertürk, "Multiplication-free One-bit Transform for Low-complexity Block-based Motion Estimation," IEEE Signal Process. Lett., vol. 14, no. 2, pp. 109-112, February 2007.
A. Akin, Y. Dogan and I. Hamzaoglu, "High Performance Hardware Architectures for One Bit Transform Based Motion Estimation," IEEE Trans. Consum. Electron., vol. 55, no. 2, pp. 941– 949, August 2009.
A. Akin, G. Sayilar and I. Hamzaoglu, "High Performance Hardware Architectures for One Bit Transform Based Single and Multiple Reference Frame Motion Estimation," IEEE Trans. Consum. Electron., vol. 56, no. 2, pp. 1144–1152, July 2010.
S. Chatterjee and I. Chakrabarti, "Low Power VLSI Architectures for One Bit Transformation Based Fast Motion Estimation," IEEE Trans. Consum. Electron., vol. 56, no.4, pp. 2652–2660, January 2011.
A. Bahari, T. Arslan and A.T. Erdogan, "Low-power H. 264 Video Compression Architectures for Mobile Communication," IEEE Trans. Circuits Syst. Video Technol., vol. 19, no. 9, pp. 1251-1261, September 2009.
I. Chakrabarti, K. Batta and S. Chatterjee, "Efficient Pixel Truncation Algorithm and Architecture," Motion Estimation for Video Coding, Studies in Computational Intelligence, Springer, vol. 590, pp. 65-83, 2015.
D. V. Manjunatha and G. Sainarayanan, "Low-Power Sum of Absolute Difference Architecture for Video Coding," Emerging Research in Electronics, Computer Science and Technol., Lecture Notes in Electrical Engineering, Springer, vol. 248, pp. 335-341, 2014.
E. AlQaralleh and O. M. F. Abu-Sharkh, "Low-complexity Motion Estimation Design Using Modified XOR Function," Springer Multimedia Tools and Applicat., DOI: 10.1007/s11042-015- 2948-z, September 2015.
G. Sanchez, M. Porto and L. Agostini, "A Hardware Friendly Motion Estimation Algorithm for the Emergent HEVC Standard and Its Low Power Hardware Design," Proc. 20th IEEE Int. Conf. Image Process., pp. 1991-1994, 2013.
M. E. Sinangil et al., "Hardware-aware Motion Estimation Search Algorithm Development for High-efficiency Video Coding (HEVC) Standard," Proc. 19th IEEE Int. Conf. Image Process., pp. 1529-1532, 2012. 152 "A Hardware-efficient Block Matching Unit for H.265/HEVC Motion Estimation Engine Using Bit-shrinking", Osama M. F. Abu-Sharkh and Esam A. AlQaralleh.
G. Sanchez et al., "DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation," Int. J. Reconfigurable Computing, vol. 2012, pp. 1-12, January 2012.
E. Jaja et al., "Efficient Motion Estimation Algorithms for HEVC/H. 265 Video Coding," Information Science and Applicat., Lecture Notes in Electrical Engineering, Springer, vol. 339, pp. 287-294, 2015.
A. Medhat et al., "Fast Center Search Algorithm with Hardware Implementation for Motion Estimation in HEVC Encoder," Proc. 21st IEEE Int. Conf. Electronics, Circuits and Systems, pp. 155-158, 2014.
K. Miyazawa et al., "Real-time Hardware Implementation of HEVC Video Encoder for 1080p HD Video," Proc. Picture Coding Symp., pp. 225-228, 2013.
G. Pastuszak and M. Trochimiuk, "Algorithm and Architecture Design of the Motion Estimation for the H. 265/HEVC 4K-UHD Encoder," Springer J. Real-Time Image Process., DOI: 10.1007/s11554-015-0516-4, July 2015.
X. Ye, D. Ding and L. Yu, "A Hardware-oriented IME Algorithm and Its Implementation for HEVC," Proc. IEEE Visual Commun. and Image Process. Conf., pp. 205-208, 2014.
JCT-VC High Efficiency Video Coding Reference Software, (2016, Mar 11), HM 16.6[ine], Available: https:/hevc.hhi.fraunhofer.de.
E. A. AlQaralleh, O. M. F. Abu-Sharkh and B. A. Y. AlQaralleh, "MATLAB/Simulink-based Verification Environment for Motion Estimation in H. 264/AVC," Proc. 5th IEEE Int. Conf. Digital Inform. and Commun. Technol. and Its Applicat., pp. 59-63, 2015.
Mathworks, (2016, Mar 11), Matlab/Simulink Users Guide, Application Program Interface Guide[ine], Available: http://www.mathworks.com.
Mentor Graphics, (2016, Mar 11), ModelSim[ine], Available: https://www.mentor.com/products/fpga/model/