NEWS
Home / Search for: FIFO buffer

A PARALLEL PIPELINED PACKET SWITCH ARCHITECTURE FOR MESH-CONNECTED MULTIPROCESSORS WITH INDEPENDENTLY ROUTED FLITS

(Received: 2019-04-27, Revised: 2019-06-30 , Accepted: 2019-07-22)
Jamil Al-Azzeh,Mohammed Agmal,Igor Zotov
#Multiprocessor #Mesh topology #Packet switching #Input-queued switch #FIFO-buffer #Flit #Pipelining #Through-put.
  • Views: 3792
  • Downloads: 977
  • DOI: 10.5455/jjcit.71-1556375171
  • Cited by: 1
Abstract

JJCIT is indexed in