C-ELEMENT DESIGN IN QUANTUM DOT CELLULAR AUTOMATA

(Received: 30-Aug.-2020, Revised: 14-Oct.-2020 , Accepted: 5-Nov.-2020)

Authors Mutaz Al-Tarawneh, Ziyad A. Altarawneh,

Keywords #QCA #Asynchronous circuits #C-Element #Robustness #Structural defects

Abstract The continuous market demands for high-performance and energy-efficient computing systems have steered the computational paradigm and technologies towards nano-scale quantum dot cellular automata (QCA). This paper presents novel simple and complex QCA-based C-element structures. The proposed structures were thoroughly analyzed based on key design parameters, such as area, energy dissipation and robustness against structural defects. Simulation results demonstrate that the proposed simple structures have achieved up to 56% and 66% improvement in area and energy dissipation, respectively. On the other hand, the complex structures have shown a profound immunity against structural defects and achieved up to 143% improvement as compared to the simple structures. The proposed C-element structures can be considered as viable blocks for asynchronous designs.

References

[1] N. B. Bousari, M. K. Anvarifard and S. Haji-Nasiri, "Improving the Electrical Characteristics of Nanoscale Triple-gate Junctionless Finfet Using Gate Oxide Engineering," AEU International Journal of Electronics and Communications, vol. 108, pp. 226 – 234, 2019.

[2] A. Razavieh, P. Zeitzoff and E. J. Nowak, "Challenges and Limitations of CMOS Scaling for FinFet and Beyond Architectures," IEEE Transactions on Nanotechnology, vol. 18, pp. 999–1004, 2019.

[3] W. Sung and Y. Li, "DC/AC/RF Characteristic Fluctuations Induced by Various Random Discrete Dopants of Gate-all-around Silicon Nanowire N-MOSFETs,” IEEE Transactions on Electron Devices, vol. 65, no. 6, pp. 2638–2646, June 2018.

[4] D. E. Nikonov and I. A. Young, "Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits," IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 1, pp. 3–11, 2015.

[5] N. K. Chaubey and B. B. Prajapati, "Quantum Cryptography and the Future of Cyber Security," Hershey, PA, USA, pp. 1–343, 2020.

[6] B. Debnath, J. C. Das, D. De, S. P. Mondal, A. Ahmadian, M. Salimi and M. Ferrara, "Security Analysis with Novel Image Masking Based Quantum-dot Cellular Automata Information Security Model," IEEE Access, vol. 8, pp. 117 159–117 172, 2020.

[7] C. S. Lent, P. D. Tougaw, W. Porod and G. H. Bernstein, "Quantum Cellular Automata," Nanotechnology, vol. 4, no. 1, pp. 49–57, Jan. 1993.

[8] H. Adepuand and I. S. Rao, "Quantum-dot Cellular Automata Technology for High-speed High-data-rate Networks," Circuits, Systems and Signal Processing, vol. 38, no. 11, pp. 5236–5252, Nov. 2019.

[9] H. M. H. Babu, Quantum Computing: A pathway to quantum logic design, IOP Publishing, [Online], Available: http://dx.doi.org/10.1088/978-0-7503-2747-3, 2020.

[10] M. Gao, J. Wang, S. Fang, J. Nan and L. Daming, "A New Nano Design for Implementation of a Digital Comparator Based on Quantum-dot Cellular Automata," International Journal of Theoretical Physics, May 2020.

[11] A. N. Bahar and K. A. Wahid, "Design and Implementation of Approximate DCT Architecture in Quantum-dot Cellular Automata," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1–10, (Early Access), 2020.

[12] Z. Song, G. Xie, X. Cheng, L. Wang and Y. Zhang, "An Ultra-low Cost Multilayer RAM in Quantum-dot Cellular Automata," IEEE Transactions on Circuits and Systems II: Express Briefs, (Early Access), pp. 1– 1, 2020.

[13] M. Goswami, A. Mondal, M. H. Mahalat, B. Sen and B. K. Sikdar, "An Efficient Clocking Scheme for Quantum-dot Cellular Automata," International Journal of Electronics Letters, vol. 8, no. 1, pp. 83–96, 2020.

[14] R. Laajimi, "Nanoarchitecture of Quantum-dot Cellular Automata (QCA) Using Small Area for Digital Circuits," Chapter 3 in Book: Advanced Electronic Circuits-Principles, Architectures and Applications on Emerging Technologies, IntechOpen, 2018.

[15] M. Raj, L. Gopalakrishnan and S.-B. Ko, "Design and Analysis of Novel QCA Full Adder-subtractor," International Journal of Electronics Letters, vol. 0, no. 0, pp. 1–14, [Online], Available: https://doi.org/10.1080/21681724.2020.1726479, 2020.

[16] A. H. Majeed, M. S. B. Zainal, E. Alkaldy and D. M. Nor, "Full Adder Circuit Design with Novel Lower Complexity XOR Gate in QCA Technology," Transactions on Electrical and Electronic Materials, vol. 21, no. 2, pp. 198–207, Apr. 2020.

[17] D. Abedi and G. Jaberipur, "Decimal Full Adders Specially Designed for Quantum-dot Cellular Automata," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 1, pp. 106–110, 2018.

[18] G. Cocorullo, P. Corsonello, F. Frustaci and S. Perri, "Design of Efficient BCD Adders in Quantum-dot Cellular Automata," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 5, pp. 575– 579, 2017.

[19] L. Xingjun, S. Zhiwei, C. Hongping and M. R. J. Haghighi, "A New Design of QCA-based Nanoscale Multiplexer and Its Usage in Communications," International Journal of Communication Systems, vol. 33, no. 4, p. e4254, 2020.

[20] J.-C. Jeon, "Designing Nanotechnology QCA–multiplexer Using Majority Function-based NAND for Quantum Computing," The Journal of Supercomputing, DOI: https://doi.org/10.1007/s11227-020-03341- 8, May 2020.

[21] T. N. Sasamal, A. K. Singh and A. Mohan, "Design of Registers and Memory in QCA," Proc. of the Quantum-dot Cellular Automata Based Digital Logic Circuits: A Design Perspective, Part of the Studies in Computational Intelligence Book Series, vol. 879, pp 119-137, Springer, 2020.

[22] A. Sadhu, K. Das, D. De and M. R. Kanjilal, "Area-delay-energy Aware SRAM Memory Cell and m x n Parallel Read/write Memory Array Design for Quantum-dot Cellular Automata," Microprocessors and Microsystems, vol. 72, p. 102944, 2020.

[23] M. Patidar and N. Gupta, "An Efficient Design of Edge-triggered Synchronous Memory Element Using Quantum-dot Cellular Automata with Optimized Energy Dissipation," Journal of Computational Electronics, vol. 19, no. 2, pp. 529–542, Jun. 2020.

[24] A. N. Bahar and K. A. Wahid, "Design of an Efficient n x n Butterfly Switching Network in Quantum-dot Cellular Automata (QCA)," IEEE Transactions on Nanotechnology, vol. 19, pp. 147–155, 2020.

[25] A. N. Bahar and K. A. Wahid, "Design of QCA-serial Parallel Multiplier (QSPM) with Energy Dissipation Analysis," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 10, pp. 1939–1943, 2020.

[26] R. Marshal, G. Lakshminarayanan, S. B. Ko, N. Naganathan and N. Ramasubramanian, "Configurable Logic Blocks and Memory Blocks for Beyond CMOS FPGA Based Embedded Systems," IEEE Embedded Systems Letters, pp. 1–1, 2020.

[27] S.-S. Ahmadpour, M. Mosleh and S. Rasouli Heikalabad, "Robust QCA Full-adders Using An Efficient Fault-tolerant Five-input Majority Gate," International Journal of Circuit Theory and Applications, vol. 47, no. 7, pp. 1037–1056, 2019.

[28] Z. Tabassam, S. R. Naqvi, T. Akram, M. Alhussein, K. Aurangzeb and S. A. Haider, "Towards Designing Asynchronous Microprocessors: From Specification to Tape-out," IEEE Access, vol. 7, pp. 33978–34003, 2019.

[29] B. Sparkman, S. C. Smith and J. Di, "Built-in Self-test for Multi-threshold Null Convention Logic Asynchronous Circuits," Proc. of the 38th IEEE VLSI Test Symposium (VTS), pp. 1–6, San Diego, USA, 2020.

[30] A. Motaqi, M. Helaoui, S. Aghli Moghaddam and M. R. Mosavi, "Detailed Implementation of Asynchronous Circuits on Commercial FPGAs," Analog Integrated Circuits and Signal Processing, vol. 103, no. 3, pp. 375–389, Jun. 2020.

[31] R. Ezz Eldin, M. A. El Moursy and H. F. A. Hamed, "Synchronous and Asynchronous NoC Design Under High Process Variation," Analysis and Design of Network-on-Chip under High Process Variation, Cham: Springer International Publishing, pp. 71–86, 2015.

[32] J. Spars and S. Furber, Principles of Asynchronous Circuit Design: A Systems Perspective, 1st Ed., Springer Publishing Company, Incorporated, 2010.

[33] A. Yakovlev, K. Gardiner and A. Bystrov, "A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits," Proc. of the 13th IEEE International On-Line Testing Symposium (IOLTS 07), pp. 223–230, Los Alamitos, CA, USA, 2007.

[34] A. de Gennaro, D. Sokolov and A. Mokhov, "Design and Implementation of Reconfigurable Asynchronous Pipelines," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 6, pp. 1527– 1539, 2020.

[35] K. Walus, T. J. Dysart, G. A. Jullien and R. A. Budiman, "QCADesigner: A Rapid Design and Simulation Tool for Quantum-dot Cellular Automata," IEEE Transactions on Nanotechnology, vol. 3, no. 1, pp. 26– 31, 2004.

[36] F. Sill Torres, R. Wille, P. Niemann and R. Drechsler, "An Energy-aware Model for the Logic Synthesis of Quantum-dot Cellular Automata," IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 37, no. 12, pp. 3031–3041, 2018.

[37] D. Reis and F. Sill Torres, "A Defects Simulator for Robustness Analysis of QCA Circuits," Journal of Integrated Circuits and Systems, vol. 11, pp. 86–96, Aug. 2016.

[38] M. Raj and L. Gopalakrishnan, "Cost Efficient Subtractor Designs in QCA," Proc. of the International Conference on Electronics and Sustainable Communication Systems (ICESC), pp. 1168–1172, Coimbatore, India, 2020.

[39] J. Maharaj and S. Muthurathinam, "Efficient Majority Logic Subtractor Design Using Multilayer Crossover in Quantum-dot Cellular Automata," Journal of Nanophotonics, vol. 14, no. 3, pp. 1 – 10.

[40] N. Soufi and S. C. Smith, "Analysis and Design of CMOS Resettable C-elements," Proc. of the 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 104–107, Boston, USA, 2017.