A. P. Deb Nath, S. Boddupalli, S. Bhunia and S. Ray, "Resilient System-on-chip Designs with NoC Fabrics," IEEE Transactions on Information Forensics and Security, vol. 15, pp. 2808–2823, 2020.
 V. S. Chakravarthi, A Practical Approach to VLSI System on Chip (SoC) Design: A Comprehensive Guide, Cham: Springer International Publishing, 2020.
 J. Kaur and S. Reddy, "SchedCust: Design and Development of Scheduling Policy Customization Framework for ARM Based System on Chip," Procedia Computer Science, vol. 171, pp. 627 – 634, 2020.
 R. Ezz Eldin, M. A. El-Moursy and H. F. A. Hamed, Network on Chip Aspects, in Book: Analysis and Design of Networks-on-Chip under High Process Variation, pp. 11–44, Cham: Springer Int. Publishing, 2015.
 R. Ezz Eldin, M. A. El-Moursy and H. F. A. Hamed, Synchronous and Asynchronous NoC Design under High Process Variation, in Book: Analysis and Design of Networks-on-Chip under High Process Variation, pp. 71–86, Cham: Springer International Publishing, 2015.
 Y. Tamir and H.-C. Chi, "Symmetric Crossbar Arbiters for VLSI Communication Switches," IEEE Transactions on Parallel and Distributed Systems, vol. 4, no. 1, pp. 13–27, 1993.
 K. A. Helal, S. Attia, T. Ismail and H. Mostafa, "Priority-select Arbiter: An Efficient Round-robin Arbiter," Proc. of the 13th IEEE Int. New Circuits and Systems Conf. (NEWCAS), pp. 1–4, Grenoble, France, 2015.
 R. Bashizade and H. Sarbazi-Azad, "P2r2: Parallel Pseudo- Round-robin Arbiter for High Performance NoCs," Integration, vol. 50, pp. 173 – 182, 2015.
 L. Liu, Z. Zhu, D. Zhou and Y. Yang, "A Fair Arbitration for Network on Chip Routing with Odd Even Turn Model," Microelectronics Journal, vol. 64, pp. 1 – 8, 2017.
 G. A. Subbarao and P. D. Hafliger, "Design and Comparison of Synthesizable Fair Asynchronous Arbiter," Proc. of the 18th IEEE International New Circuits and Systems Conference (NEWCAS), pp. 122–125, Montreal, QC, Canada, 2020.
 S. Golubcovs, A. Mokhov, A. Bystrov, D. Sokolov and A. Yakovlev, "Generalized Asynchronous Arbiter," Proc. of the 19th IEEE International Conference on Application of Concurrency to System Design (ACSD), pp. 3–12, Aachen, Germany, 2019.
 D. E. Nikonov and I. A. Young, "Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits," IEEE Journal on Exploratory Solid-state Computational Devices and Circuits, vol. 1, pp. 3–11, 2015.
 A. Razavieh, P. Zeitzoff and E. J. Nowak, "Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures," IEEE Transactions on Nanotechnology, vol. 18, pp. 999–1004, 2019.
 H. Adepuand and I. S. Rao, "Quantum-dot Cellular Automata Technology for High-speed High-data-rate Networks," Circuits, Systems and Signal Processing, vol. 38, no. 11, pp. 5236–5252, Nov. 2019.
 H. M. H. Babu, Quantum Computing, Ser. 2053-2563, IOP Publishing, [Online], Available: http://dx.doi.org/10.1088/978-0-7503-2747-3, 2020.
 M. Al-Tarawneh and Z. Altarawneh, "C-element Design in Quantum Dot Cellular Automata," Jordanian Journal of Computers and Information Technology (JJCIT), vol. 7, no. 1, pp. 51–63, March 2021.
 A. H. Majeed, "Quantum-dot Cellular Automata-based Superior Design of Conservative Reversible Parity Logic Circuits," Jordanian Journal of Computers and Information Technology (JJCIT), vol. 7, no. 1, pp. 39– 50, March 2021.
 T. N. Sasamal, A. K. Singh and A. Mohan, Clocking Schemes for QCA, in Book: Quantum-dot Cellular Automata Based Digital Logic Circuits: A Design Perspective, pp. 139–145, Springer, Singapore, 2020.
 M. Goswami, A. Mondal, M. H. Mahalat, B. Sen and B. K. Sikdar, "An Efficient Clocking Scheme for Quantum-dot Cellular Automata," Int. Journal of Electronics Letters, vol. 8, no. 1, pp. 83–96, 2020.
 M. A. Tehrani, F. Safaei, M. H. Moaiyeri and K. Navi, "Design and Implementation of Multistage Interconnection Networks Using Quantum-dot Cellular Automata," Microelectronics Journal, vol. 42, no. 6, pp. 913 – 922, 2011.
 S. Das and D. De, "Nanocommunication Using QCA: A Data Path Selector CUM Router for Efficient Channel Utilization," Proc. of the IEEE International Conference on Radar, Communication and Computing (ICRCC), 2012, pp. 43–47, Tiruvannamalai, India, 2012.
 L. H. B. Sardinha, A. M. M. Costa, O. P. V. Neto, L. F. M. Vieira and M. A. M. Vieira, "Nanorouter: A Quantum-dot Cellular Automata Design," IEEE Journal on Selected Areas in Communications, vol. 31, no. 12, pp. 825–834, 2013.
 A. Kamaraj, Abinaya and S. Ramya, "Design of Router Using Reversible Logic in Quantum Cellular Automata," Proc. of the IEEE International Conference on Communication and Network Technologies, pp. 249–253, Sivakasi, India, 2014.
 D. Silva, L. Sardinha, M. Vieira, L. Vieira and O. Vilela Neto, "Robust Serial Nanocommunication with QCA," IEEE Transactions on Nanotechnology, vol. 14, no. 3, pp. 464–472, 2015.
 J. C. Das, D. De, S. P. Mondal, A. Ahmadian, F. Ghaemi and N. Senu, "QCA Based Error Detection Circuit for Nano Communication Network," IEEE Access, vol. 7, pp. 67 355–67 366, 2019.
 J. R. Monfared and A. Mousavi, "Design and Simulation of Nano-arbiters Using Quantum-dot Cellular Automata," Microprocessors and Microsystems, vol. 72, p. 102926, 2020.
 Y. Yang, R. Wu, L. Zhang and D. Zhou, "An Asynchronous Adaptive Priority Round-robin Arbiter Based on Four-phase Dual-rail Protocol," Chinese Journal of Electronics, vol. 24, no. 1, pp. 1–7, 2015.
 A. Monemi, C. Y. Ooi, M. Palesi and M. N. Marsono, "Ping-lock Round Robin Arbiter," Microelectronics Journal, vol. 63, pp. 81 – 93, 2017.
 M. M. Abutaleb, "QCAPUF: QCA-based Physically Unclonable Function as a Hardware Security Primitive," Semiconductor Science and Technology, vol. 33, no. 4, p. 045011, Mar. 2018.
 V. Vankamamidi, M. Ottavi and F. Lombardi, "Two-dimensional Schemes for Clocking/Timing of QCA Circuits," IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 27, no. 1, pp. 34–44, 2008.
 A. Roohi, R. Zand, S. Angizi and R. F. DeMara, "A Parity-preserving Reversible QCA Gate with Self-checking Cascadable Resiliency," IEEE Transactions on Emerging Topics in Computing, vol. 6, no. 4, pp. 450– 459, 2018.
 K. Walus, T. J. Dysart, G. A. Jullien and R. A. Budiman, "QCADesigner: A Rapid Design and Simulation Tool for Quantum-dot Cellular Automata," IEEE Transactions on Nanotechnology, vol. 3, no. 1, pp. 26–31, 2004.
 F. Sill Torres, R. Wille, P. Niemann and R. Drechsler, "An Energy-aware Model for the Logic Synthesis of Quantum-dot Cellular Automata," IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 37, no. 12, pp. 3031–3041, 2018.